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74HC173 Datasheet PDF

Part Series:
74HC173 Series
Category:
Logic ICs
Description:
IC D-TYPE POS TRG SNGL 16SOIC
Updated Time: 2023/01/13 02:21:52 (UTC + 8)

74HC173 Datasheet PDF Logic ICs

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IC D-TYPE POS TRG SNGL 16SOIC
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IC D-TYPE POS TRG SNGL 16SSOP
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Flip Flop D-Type Bus Interface Pos-Edge 3-ST 1Element 16Pin TSSOP Tube
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Flip Flop D-Type Bus Interface Pos-Edge 3-ST 1Element 16Pin SSOP T/R
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Flip Flop D-Type Bus Interface Pos-Edge 3-ST 1Element 16Pin SSOP Tube
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IC HC/UH SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, TRUE OUTPUT, PDSO16, SOT-109, SO-16, FF/Latch
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74HC(T)173 - Quad D-type flip-flop; positive-edge trigger; 3-state DIP 16Pin

74HC173D,652 - Nexperia Specifications

TYPE
DESCRIPTION
Mounting Style
Surface Mount
Frequency
88 MHz
Number of Pins
16 Pin
Case/Package
SOIC-16
Number of Outputs
4 Output
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74HC173D,652 - Nexperia Function Overview

The 74HC173D is a quad positive-edge trigger D-type Flip-flop with 3-state outputs. This high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). This 4-bit parallel load register with clock enable control, 3-state buffered outputs (Q0 to Q3) and master reset (MR). When the two data enable inputs (E1\ and E2\\) are low, the data on the Dn inputs is loaded into the register synchronously with the low-to-high clock transition. When one or both En\ inputs are high one set-up time prior to the low-to-high clock transition, the register will retain the previous data. Data inputs and clock enable inputs are fully edge-triggered and must be stable only one set-up time prior to the low-to-high clock transition. The master reset input (MR) is an active high asynchronous input. When MR is high, all four flip-flops are reset (cleared) independently of any other input condition.
Gated input enable for hold (do nothing) mode
Gated output enable control
Edge-triggered D-type register
Asynchronous master reset
Bus driver output capability
Complies with JEDEC standard No. 7A
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