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74HC7046 Datasheet PDF

Part Series:
74HC7046 Series
Category:
Clock & Timing
Description:
74HC(T)7046A - Phase-locked-loop with lock detector SOP 16Pin
Updated Time: 2023/01/13 03:14:54 (UTC + 8)

74HC7046 Datasheet PDF Clock & Timing

38 Pages
NXP
IC PHASE LOCKED LOOP, PDSO16, PLASTIC, SSOP-16, PLL or Frequency Synthesis Circuit
38 Pages
NXP
74HC(T)7046A - Phase-locked-loop with lock detector SSOP1 16Pin
38 Pages
NXP
74HC(T)7046A - Phase-locked-loop with lock detector SSOP1 16Pin
38 Pages
NXP
Ic Pll w/Lock Detector 16soic

74HC7046AD,112 - NXP Specifications

TYPE
DESCRIPTION
Mounting Style
Surface Mount
Frequency
19 MHz
Number of Pins
16 Pin
Supply Voltage (DC)
3.00V (min)
Case/Package
SOIC-16
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74HC7046AD,112 - NXP Function Overview

The 74HC7046AD,112 is a high-speed Si-gate CMOS Device specified in compliance with JEDEC standard no. 7. The 74HC/HCT7046 is phase-locked-loop circuit that comprises a linear voltage-controlled oscillator (VCO) and two different phase comparators (PC1 and PC2) with a common signal input amplifier and a common comparator input. A lock detector is provided and this gives a HIGH level at pin 1 (LD) when the PLL is locked. The lock detector capacitor must be connected between pin 15 (CLD) and pin 8 (GND). The input signal can be directly coupled to large voltage signals or indirectly coupled (with a series capacitor) to small voltage signals. A self-bias input/circuit keeps small voltage signals within the linear region of the input amplifiers. With a passive low-pass filter, the "7046" forms a second-order loop PLL. The excellent VCO linearity is achieved by the use of linear op-amp techniques.
Low power consumption
Excellent VCO frequency linearity
VCO-inhibit control for ON/OFF keying and for low standby power consumption
Minimal frequency drift
Zero voltage offset due to op-amp buffering
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