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74HCT164 Datasheet PDF

Part Series:
74HCT164 Series
Category:
Logic ICs
Description:
IC SHIFT REG 8Bit SI-PO 14SOIC
Updated Time: 2023/01/13 02:28:34 (UTC + 8)

74HCT164 Datasheet PDF Logic ICs

21 Pages
Nexperia
IC SHIFT REG 8Bit SI-PO 14TSSOP
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NXP
NXP 74HCT164D,653 Shift Register, HCT Family, 74HCT164, Serial to Parallel, 1Element, 8Bit, SOIC, 14Pins
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74HCT Series 5V 8Bit Serial-In Parallel-Out Shift Register SMT - TSSOP-14
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IC 8Bit SHIFT REGISTER 14-DHVQFN
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Nexperia
IC SHIFT REG 8Bit SI-PO 14TSSOP
21 Pages
NXP
IC 8Bit SHIFT REGISTER 14-SOIC
21 Pages
Diodes
Shift Register Single 8Bit Serial to Parallel 14Pin TSSOP T/R
21 Pages
Nexperia
IC SHIFT REG 8Bit SI-PO 14TSSOP
20 Pages
Nexperia
IC 8Bit SHIFT REGISTER 14-SOIC
20 Pages
NXP
Shift Register Single 8Bit Serial to Parallel 14Pin PDIP Bulk
20 Pages
Nexperia
Shift Register Single 8Bit Serial to Parallel 14Pin TSSOP
20 Pages
NXP
Shift Register Single 8Bit Serial to Parallel 14Pin TSSOP Tube
19 Pages
NXP
Shift Register Single 8Bit Serial to Parallel 14Pin SSOP Tube
19 Pages
Nexperia
IC SHIFT REG 8Bit SI-PO 14SOIC
19 Pages
NXP
Shift Register Single 8Bit Serial to Parallel 14Pin TSSOP T/R
10 Pages
Diodes
Shift Register Single 8Bit Serial to Parallel 14Pin PDIP Tube

74HCT164D,653 - Nexperia Specifications

TYPE
DESCRIPTION
Mounting Style
Surface Mount
Number of Pins
14 Pin
Case/Package
SOIC-14
Number of Outputs
8 Output
Number of Channels
8 Channel
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74HCT164D,653 - Nexperia Function Overview

The 74HCT164D is a 8-bit serial-in/parallel-out Shift Register features two serial data inputs (DSA and DSB), eight parallel data outputs (Q0 to Q7). Data is entered serially through DSA or DSB and either input can be used as an active high enable for data entry through the other input. Data is shifted on the low-to-high transitions of the clock (CP) input. A low on the master reset input (MR) clears the register and forces all outputs low, independently of other inputs. Inputs include clamp diodes. This enables the use of current limiting resistors to interface inputs to voltages in excess of VCC.
TTL Input level
Gated serial data inputs
Asynchronous master reset
Complies with JEDEC standard No. 7A
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