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CD4017 Datasheet PDF

Part Series:
CD4017 Series
Category:
Logic ICs
Description:
Counter / Divider, 11MHz, 3V to 18V, DIP-16
Updated Time: 2023/01/13 01:18:56 (UTC + 8)

CD4017 Datasheet PDF Logic ICs

31 Pages
TI
Flip Flop D-Type Bus Interface Pos-Edge 1Element 16Pin CDIP Tube
20 Pages
TI
Decade Counter / Divider, 11MHz, 1 Gate, 1Input, 3V to 18V, DIP-16
20 Pages
TI
Flip Flop D-Type Bus Interface Pos-Edge 1Element 16Pin SOP T/R
20 Pages
TI
TEXAS INSTRUMENTS CD4017BEE4 Counter / Divider, 11MHz, 3V to 18V, DIP-16
19 Pages
TI
Counter / Divider, 11MHz, 3V to 18V, DIP-16
19 Pages
TI
TEXAS INSTRUMENTS CD4017BM Counter / Divider, 11MHz, 3V to 18V, DIP-16
19 Pages
TI
Flip-Flop, Complementary, Positive Edge, CD40175, D, 70ns, 14MHz, 6.8mA, DIP
19 Pages
TI
TEXAS INSTRUMENTS CD4017BPWR Counter / Divider, 11MHz, 3V to 18V, TSSOP-16
19 Pages
TI
Logic IC - Counter Texas Instruments CD4017BPW Counter, Tenth 4000B Positive slope 5.5MHz TSSOP 16
19 Pages
TI
TEXAS INSTRUMENTS CD4017BNSR Decade Counter, 11MHz, 10Bit, 3V to 18V, SOIC-16
19 Pages
TI
Flip Flop D-Type Bus Interface Pos-Edge 1Element 16Pin TSSOP T/R
19 Pages
TI
Counter/Divider Single 5Bit Decade UP 16Pin CDIP Tube
18 Pages
TI
TEXAS INSTRUMENTS CD40174BE Flip-Flop, Non Inverted, Positive Edge, CD40174, D, 50ns, 8MHz, 6.8mA, DIP
18 Pages
TI
TEXAS INSTRUMENTS CD40175BM Flip-Flop, Complementary Output, Positive Edge, CD40175, D, 70ns, 14MHz, 6.8mA, SOIC
18 Pages
TI
Flip Flop D-Type Bus Interface Pos-Edge 1Element 16Pin SOIC T/R
16 Pages
TI
TEXAS INSTRUMENTS CD40174BPW Flip-Flop, CD40174, D, 50ns, 16MHz, 6.8mA, TSSOP

CD4017BM96 - TI Specifications

TYPE
DESCRIPTION
Mounting Style
Surface Mount
Frequency
11 MHz
Number of Pins
16 Pin
Supply Voltage (DC)
3.00V (min)
Case/Package
SOIC-16
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CD4017BM96 - TI Function Overview

The CD4017BM96 is a CMOS Decade Counter with 10 decoded outputs. Inputs include a clock, reset and clock inhibit signal. Schmitt trigger action in the clock input circuit provides pulse shaping that allows unlimited clock input pulse rise and fall times. It is advanced one count at the positive clock signal transition if the clock inhibit signal is low. Counter advancement via the clock line is inhibited when the clock inhibit signal is high. A high reset signal clears the counter to its zero count. Use of the Johnson counter configuration permits high-speed operation, 2-input decode-gating and spike-free decoded outputs. Anti-lock gating is provided, thus assuring proper counting sequence. The decoded output is normally low and go high only at their respective decoded time slot. Each decoded output remains high for one full clock cycle. A carry-out signal completes on cycle every 10 clock input cycles and is used to ripple-clock the succeeding device in a multi-device counting chain.
Fully static operation
Standardized, symmetrical output characteristics
100% Tested for quiescent current at 20V
Green product and no Sb/Br
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