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CD4076 Datasheet PDF

Part Series:
CD4076 Series
Category:
Flip Flops
Description:
TEXAS INSTRUMENTS CD4076BE Shift Register, D Type, CD4076, 1Element, 4Bit, DIP, 16Pins
Updated Time: 2023/01/13 03:01:19 (UTC + 8)

CD4076 Datasheet PDF Flip Flops

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TI
TEXAS INSTRUMENTS CD4076BE Shift Register, D Type, CD4076, 1Element, 4Bit, DIP, 16Pins
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Flip Flop D-Type Bus Interface Pos-Edge 3-ST 1Element 16Pin SOP T/R
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Flip Flop D-Type Bus Interface Pos-Edge 3-ST 1Element 16Pin SOP T/R
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Flip Flop D-Type Bus Interface Pos-Edge 3-ST 1Element 16Pin SOIC T/R
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Flip Flop D-Type Bus Interface Pos-Edge 3-ST 1Element 16Pin SOIC T/R
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Flip Flop D-Type Bus Interface Pos-Edge 3-ST 1Element 16Pin TSSOP T/R
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CMOS 4Bit D-Type Registers with Clock and 3-State Outputs 16-TSSOP -55 to 125
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CMOS 4Bit D-Type Registers with Clock and 3-State Outputs 16-TSSOP -55 to 125
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CMOS 4Bit D-Type Registers with Clock and 3-State Outputs 16-SOIC -55 to 125

CD4076BE - TI Specifications

TYPE
DESCRIPTION
Mounting Style
Through Hole
Frequency
8 MHz
Number of Pins
16 Pin
Supply Voltage (DC)
15.0 V, 18.0 V (max)
Case/Package
DIP-16
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CD4076BE - TI Function Overview

The CD4076BE is a 4-bit CMOS D-type Register with clock and 3-state outputs. Data disable inputs are provided to control the entry of data into the flip-flops. When both data disable inputs are low, data at the D inputs are loaded into their respective flip-flops on the next positive transition of the clock input. Output disable inputs are also provided. When the output disable inputs are both low, the normal logic states of the four outputs are available to the load. The outputs are disabled independently of the clock by a high logic level at either output disable input and present a high impedance.
Three-state outputs
Input disabled without gating the clock
Gated output control lines for enabling or disabling the outputs
Standardized, symmetrical output characteristics
100% Tested for quiescent current at 20V
Maximum input current of 1µA at 18V
±10mA DC input current
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