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CD4081 Datasheet PDF

Part Series:
CD4081 Series
Category:
Logic Gates
Description:
AND Gate 4Element 2IN CMOS 14Pin TSSOP T/R
Updated Time: 2023/01/13 01:26:29 (UTC + 8)

CD4081 Datasheet PDF Logic Gates

31 Pages
TI
AND Gate 4Element 2IN CMOS 14Pin TSSOP T/R
31 Pages
TI
AND Gate 4Element 2IN CMOS 14Pin TSSOP Tube
31 Pages
TI
AND Gate 4Element 2IN CMOS 14Pin SOP T/R
31 Pages
TI
AND Gate 4Element 2IN CMOS 14Pin SOIC T/R
31 Pages
TI
AND Gate 4Element 2IN CMOS 14Pin SOIC Tube
31 Pages
TI
AND Gate 4Element 2IN CMOS 14Pin TSSOP Tube
31 Pages
TI
AND Gate 4Element 2IN CMOS 14Pin TSSOP T/R
31 Pages
TI
AND Gate 4Element 2IN CMOS 14Pin SOIC Tube
31 Pages
TI
AND Gate 4Element 2IN CMOS 14Pin SOIC T/R
31 Pages
TI
AND Gate 4Element 2IN CMOS 14Pin SOIC T/R
31 Pages
TI
AND Gate 4Element 2IN CMOS 14Pin SOP T/R
30 Pages
TI
AND Gate 4Element 2IN CMOS 14Pin CDIP Tube
30 Pages
TI
AND Gate 4Element 2IN CMOS 14Pin CDIP Tube
10 Pages
Fairchild
AND Gate 4Element 2IN CMOS 14Pin PDIP W Rail
10 Pages
Fairchild
AND Gate 4Element 2IN CMOS 14Pin SOIC N Rail
10 Pages
Fairchild
AND Gate 4Element 2IN CMOS 14Pin SOIC N T/R

CD4081BPWR - TI Specifications

TYPE
DESCRIPTION
Mounting Style
Surface Mount
Number of Pins
14 Pin
Supply Voltage (DC)
3.00V ~ 18.0V
Case/Package
TSSOP-14
Number of Outputs
1 Output
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CD4081BPWR - TI Function Overview

The CD4081BPWR is a CMOS quad 2-input AND Gate. The device provides the system designer with direct implementation of the AND function and supplement the existing family of CMOS gates. The device features standardized symmetrical output characteristics.
Medium-speed operation 60ns at VDD = 10V
100% Tested for quiescent current at 20V
Maximum input current of 1µA at 18V
2.5V at VDD = 15V Noise margin
5V, 10V and 15V Parametric ratings
Meets all requirements of JEDEC tentative standard No. 13B
Green product and no Sb/Br
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