Web Analytics
Part Datasheet Search > Counters > CD4516 Datasheet PDF
Images are for reference

CD4516 Datasheet PDF

Part Series:
CD4516 Series
Category:
Counters
Description:
Logic IC - Counter Texas Instruments 4516 Binary counter 4000B Positive slope 11MHz PDIP 16
Updated Time: 2023/01/13 02:05:28 (UTC + 8)

CD4516 Datasheet PDF Counters

19 Pages
TI
Counter Single 4Bit Sync Binary UP/Down 16Pin TSSOP Tube
17 Pages
TI
Logic IC - Counter Texas Instruments 4516 Binary counter 4000B Positive slope 11MHz PDIP 16
17 Pages
TI
Counter Single 4Bit Sync Binary UP/Down 16Pin PDIP Tube
16 Pages
TI
Counter Single 4Bit Sync Binary UP/Down 16Pin CDIP Tube
16 Pages
TI
Counter Single 4Bit Sync Binary UP/Down 16Pin TSSOP T/R
16 Pages
TI
CMOS Presettable Binary Up/Down Counter 16-TSSOP -55 to 125
16 Pages
TI
Counter Single 4Bit Sync Binary UP/Down 16Pin TSSOP Tube
16 Pages
TI
CMOS Presettable Binary Up/Down Counter 16-SO -55 to 125
16 Pages
TI
CMOS Presettable Binary Up/Down Counter 16-SO -55 to 125

CD4516BE - TI Specifications

TYPE
DESCRIPTION
Mounting Style
Through Hole
Number of Pins
16 Pin
Supply Voltage (DC)
3.00V ~ 18.0V
Case/Package
DIP-16
Number of Outputs
4 Output
show more

CD4516BE - TI Function Overview

The CD4516BE is a CMOS presettable binary Up/Down Counter consists of four synchronously clocked D-type flip-flops connected as counters. This counter can be cleared by a high level on the RESET line and can be pre-set to any binary number present on the jam inputs by a high level on the PRESET ENABLE line. If the CARRY-IN input is held low, the counter advances up or down on each positive-going clock transition. Synchronous cascading is accomplished by connecting all clock inputs in parallel and connecting the CARRY-OUT of a less significant stage to the CARRY-IN of a more significant stage. The CD4516B can be cascaded in the ripple mode by connecting the CARRY-OUT to the clock of the next stage. If the UP/DOWN input changes during a terminal count, the CARRY-OUT must be gated with the clock and the UP/DOWN input must change while the clock is high. This method provides a clean clock signal to the subsequent counting stage.
Synchronous internal carry propagation
Reset and Preset capability
100% Tested for quiescent current at 20V
Standardized, symmetrical output characteristics
Meets all requirements of JEDEC tentative standard #13B
show more
Part Datasheet PDF Search
Loading...
72,405,303 Parts Datasheet PDF, Update more than 5,000 PDF files ervery day.

Relate Parts