74HC137D,652 Datasheet PDF - NXP

●The 74HC137D is a 3-to-8 inverting Decoder/Demultiplexer with address latches. This high-speed Si-gate CMOS device is pin compatible with low power Schottky TTL (LSTTL). It latches at the three address inputs (An). It essentially combines the 3-to-8 decoder function with a 3-bit storage latch. When the latch is enabled (LE\ = low), it acts as a 3-to-8 active low decoder. When the LE\ goes from low-to-high, the last data present at the inputs before this transition, is stored in the latches. Further address changes are ignored as long as LE\ remains high. The output enable input (E1\ and E2) controls the state of the outputs independent of the address inputs or latch operation. All outputs are high unless E1\ is low and E2 is high. The 74HC137 is ideally suited for implementing non-overlapping decoders in 3-state systems and strobed (stored address) applications in bus oriented systems.

● Multiple input enable for easy expansion or independent controls

● Active low mutually exclusive outputs

● Low-power dissipation

● Complies with JEDEC standard No. 7A