74HC175PW,118 Datasheet PDF - NXP

●The 74HC175PW is a quad positive-edge triggered D-type flip-flop with individual data inputs (Dn) and complementary outputs (Qn and Qn\\). The common clock and master reset (MR\\) inputs load and reset all flip-flops simultaneously. The D-input that meets the set-up and hold time requirements on the low-to-high clock transition will be stored in the flip-flop and appear at the Q output. A low on MR\ causes the flip-flops and outputs to be reset low. Inputs include clamp diodes. This enables the use of current limiting resistors to interface inputs to voltages in excess of VCC.

● Four edge-triggered D-type flip-flops

● Asynchronous master reset

● CMOS Input levels

● Complies with JEDEC standard No. 7A