74HC4015D,652 Datasheet PDF - NXP

●The 74HC4015D is a 4-bit dual serial-in/parallel-out Shift Register pin compatible with the 4015 of the 4000B series. Each shift register has a serial data input (1D and 2D), a clock input (1CP and 2CP), four fully buffered parallel outputs (1Q0 to 1Q3 and 2Q0 to 2Q3) and an overriding asynchronous master reset (1MR and 2MR). Information present on nD is shifted to the first register position and all data in the register is shifted one position to the right on the low-to-high transition of nCP. A high on nMR clears the register and forces nQ0 to nQ3 to low, independent of nCP and nD.

● Standard output capability

● Complies with JEDEC standard No. 7A