●General description
●The 74LVC3G07 provides three non-inverting buffers. The output of the device is an open-drain and can be connected to other open-drain outputs to implement active-LOW wired-OR or active-HIGH wired-AND functions. Input can be driven from either 3.3 V or 5 V devices. This feature allows the use of this device in a mixed 3.3 V and 5 V environment.
●Schmitt trigger action at all inputs makes the circuit tolerant for slower input rise and fall time.
●This device is fully specified for partial power-down applications using IOFF. The IOFF circuitry disables the output, preventing the damaging backflow current through the device when it is powered down.
●Features
●■ Wide supply voltage range from 1.65 V to 5.5 V
●■ 5 V tolerant input/output for interfacing with 5 V logic
●■ High noise immunity
●■ Complies with JEDEC standard:
● ◆ JESD8-7 (1.65 V to 1.95 V)
● ◆ JESD8-5 (2.3 V to 2.7 V)
● ◆ JESD8-B/JESD36 (2.7 V to 3.6 V).
●■ ESD protection:
● ◆ HBM EIA/JESD22-A114-B exceeds 2000 V
● ◆ MM EIA/JESD22-A115-A exceeds 200 V.
●■ −24 mA output drive (VCC = 3.0 V)
●■ CMOS low power consumption
●■ Latch-up performance exceeds 250 mA
●■ Direct interface with TTL levels
●■ Inputs accept voltages up to 5 V
●■ Multiple package options
●■ Specified from −40 °C to +85 °C and −40 °C to +125 °C.
