●Product Details
●The AD5684, a member of the _nano_DAC+™ family, is a low power, quad, 12-bit buffered voltage output DAC. The device includes a gain select pin giving a full-scale output of 2.5 V (gain = 1) or 5 V (gain = 2). The device operates from a single 2.7 V to 5.5 V supply, is guaranteed monotonic by design, and exhibits less than 0.1% FSR gain error and 1.5 mV offset error performance. The device is available in a 3 mm × 3 mm LFCSP and a TSSOP package.
●The AD5684 also incorporates a power-on reset circuit and a RSTSEL pin that ensures that the DAC outputs power up to zero scale or midscale and remain at that level until a valid write takes place. Each part contains a per-channel power-down feature that reduces the current consumption of the device to 4 μA at 3 V while in power-down mode.
●The AD5684 employs a versatile SPI interface that operates at clock rates up to 50 MHz, and all devices contain a VLOGIC pin intended for 1.8 V/3 V/5 V logic.
●Product Highlights
● 1. High Relative Accuracy (INL): ±1 LSB maximum
● 2. Excellent DC Performance.
●Total unadjusted error: ±0.1% of FSR maximum
●Offset error: ±1.5 mV maximum
●Gain error: ±0.1% of FSR maximum
● 3. Two Package Options: 3 mm × 3 mm, 16-lead LFCSP and 16-lead TSSOP
●Applications
● Digital gain and offset adjustment
● Programmable attenuators
● Process control (PLC I/O cards)
● Industrial automation
● Data acquisition systems
●### Features and Benefits
● High relative accuracy (INL): ±1 LSB maximum @ 12 bits
● Tiny package: 3 mm × 3 mm, 16-lead LFCSP
● Total unadjusted error (TUE): ±0.1% of FSR maximum
● Offset error: ±1.5 mV maximum
● Gain error: ±0.1% of FSR maximum
● High drive capability: 20 mA, 0.5 V from supply rails
● User selectable gain of 1 or 2 (GAIN pin)
● Reset to zero scale or midscale (RSTSEL pin)
● 1.8 V logic compatibility
● 50 MHz SPI with readback or daisy chain
● Low glitch: 0.5 nV-sec
● Low power: 1.8 mW at 3 V
● 2.7 V to 5.5 V power supply
● −40°C to +105°C temperature range
Part 3D Model
