●Product Details
●The AD9554 is a low loop bandwidth clock translator that provides jitter cleanup and synchronization for many systems, including synchronous optical networks (SONET/SDH). The AD9554 generates an output clock synchronized to up to four external input references. The digital PLL (DPLL) allows for reduction of input time jitter or phase noise associated with the external references. The digitally controlled loop and holdover circuitry of the AD9554 continuously generates a low jitter output clock even when all reference inputs have failed.
●The AD9554 operates over an industrial temperature range of −40°C to +85°C. If a smaller device is needed, the AD9554-1 is a version of this device with one output per PLL. If a single or dual DPLL version of this device is needed, refer to the AD9557 or AD9559, respectively.
●Applications
● Network synchronization, including synchronous Ethernet and synchronous digital hierarchy (SDH) to optical transport network (OTN) mapping/demapping
● Cleanup of reference clock jitter
● SONET/SDH clocks up to OC-192, including FEC
● Stratum 3 holdover, jitter cleanup, and phase transient control
● Cable infrastructure
● Data communications
● Professional video
●### Features and Benefits
● Supports GR-1244 Stratum 3 stability in holdover mode
● Supports smooth reference switchover with virtually no disturbance on output phase
● Supports Telcordia GR-253 jitter generation, transfer, and tolerance for SONET/SDH up to OC-192 systems
● Supports ITU-T G.8262 synchronous Ethernet slave clocks
● Supports ITU-T G.823, ITU-T G.824, ITU-T G.825, and ITU-T G.8261
● Auto/manual holdover and reference switchover
● Adaptive clocking allows dynamic adjustment of feedback dividers for use in OTN mapping/demapping applications
● Quad digital phase-locked loop (DPLL) architecture with four reference inputs (single-ended or differential)
● 4 × 4 crosspoint allows any reference input to drive any PLL
● Input reference frequencies from 2 kHz to 1000 MHz Reference validation and frequency monitoring: 2 ppm
● Programmable input reference switchover priority 20-bit programmable input reference divider
● 8 differential clock outputs with each differential pair configurable as HCSL, LVDS-compatible, or LVPECL-compatible
● Output frequency range: 430 kHz to 941 MHz
● Programmable 18-bit integer and 24-bit fractional feedback divider in digital PLL
● Programmable loop bandwidths from 0.1 Hz to 4 kHz
● Optional off-chip EEPROM to store power-up profile
● 72-lead (10 mm × 10 mm) LFCSP package
Part 3D Model
