AD9554BCPZ-REEL Datasheet PDF - ADI

● Supports GR-1244 Stratum 3 stability in holdover mode

● Supports smooth reference switchover with virtually nodisturbance on output phase

● Supports Telcordia GR-253 jitter generation, transfer, andtolerance for SONET/SDH up to OC-192 systems

● Supports ITU-T G.8262 synchronous Ethernet slave clocks

● Supports ITU-T G.823, ITU-T G.824, ITU-T G.825, andITU-T G.8261

● Auto/manual holdover and reference switchover

● Adaptive clocking allows dynamic adjustment of feedbackdividers for use in OTN mapping/demapping applications

● Quad digital phase-locked loop (DPLL) architecture with fourreference inputs (single-ended or differential)

● 4 × 4 crosspoint allows any reference input to drive any PLL

● Input reference frequencies from 2 kHz to 1000 MHz

● Reference validation and frequency monitoring: 2 ppm

● Programmable input reference switchover priority

● 20-bit programmable input reference divider

● 8 differential clock outputs with each differential pairconfigurable as HCSL, LVDS-compatible, or LVPECLcompatible

● Output frequency range: 430 kHz to 941 MHz

● Programmable 18-bit integer and 24-bit fractional feedbackdivider in digital PLL

● Programmable loop bandwidths from 0.1 Hz to 4 kHz

● Optional off-chip EEPROM to store power-up profile

● 72-lead (10 mm × 10 mm) LFCSP package