ADC141S626CIMM/NOPB Datasheet PDF - TI

●The ADC141S626 is a 14-bit, 50 kSPS to 250 kSPS sampling Analog-to-Digital (A/D) converter. The converter is based on a successive-approximation register (SAR) architecture where the differential nature of the analog inputs is maintained from the internal sample-and-hold circuits throughout the A/D converter to provide excellent common-mode signal rejection. The ADC141S626 features an external reference that can be varied from 1.0V to VA. It also features a zero-power track mode where the ADC is consuming the minimum amount of supply current while the internal sampling capacitor is tracking the applied analog input voltage.

●The serial data output is binary 2"s complement and is compatible with several standards, such as SPI™, QSPI™, MICROWIRE, and many common DSP serial interfaces. The conversion result is clocked out by the serial clock input and is the result of the conversion currently in progress; thus, ADC141S626 has no latency.

●The ADC141S626 may be operated with independent analog (VA) and digital input/output (VIO) supplies. VA and VIO can range from 2.7V to 5.5V and can be set independent of each other. This allows a user to maximize performance and minimize power consumption by operating the analog portion of the ADC at a VA of 5V while communicating with a 3V controller on the digital side. With a 3V source, the power consumption when operating at 200 kSPS is 2.0 mW. With a 5V source, the power consumption when operating at 250 kSPS is 4.8 mW. The power consumption drops down to 4 µW and 13 µW respectively when the ADC141S626 enters acquisition (power-down) mode. The differential input, low power consumption, and small size make the ADC141S626 ideal for direct connection to bridge sensors and transducers in battery operated systems or remote data acquisition applications.

●Operation is guaranteed over the temperature range of −40°C to +85°C and clock rates of 0.9 MHz to 4.5 MHz. The ADC141S626 is available in a 10-lead VSSOP package.