ADCLK944BCPZ-WP Datasheet PDF - ADI

●The ADCLK944BCPZ-WP is an ultrafast clock Fanout Buffer designed for high speed applications requiring low jitter. The device has a differential input equipped with center-tapped, differential, 100R on-chip termination resistors. The input can accept dc-coupled LVPECL, CML, 3.3V CMOS (single-ended) and ac-coupled 1.8V CMOS, LVDS and LVPECL inputs. A VREF pin is available for biasing ac-coupled inputs. The ADCLK944 features four full-swing emitter-coupled logic (ECL) output drivers. For LVPECL (positive ECL) operation, bias VCC to the positive supply and VEE to ground. For ECL operation, bias VCC to ground and VEE to the negative supply. The ECL output stages are designed to directly drive 800mV each side into 50R terminated to VCC-2V for a total differential output swing of 1.6V.

● On-chip input terminations

● 50fs RMS Broadband random jitter