ADN2915ACPZ Datasheet PDF - ADI

●The ADN2915ACPZ is a Clock and Data Recovery IC with integrated limiting amplifier/equalizer. The ADN2915 provides the receiver functions of quantization, signal level detect and clock and data recovery for continuous data rates from 6.5Mbps to 11.3Gbps. The ADN2915 automatically locks to all data rates without the need for an external reference clock or programming. ADN2915 jitter performance exceeds all jitter specifications required by SONET/SDH, including jitter transfer, jitter generation and jitter tolerance. The ADN2915 provides manual or automatic slice adjust and manual sample phase adjusts. Additionally, the user can select a limiting amplifier, equalizer or bypass at the input. The equalizer is either adaptive or can be manually set. The receiver front-end loss of signal (LOS) detector circuit indicates when the input signal level has fallen below user-programmable threshold. The LOS detect circuit has hysteresis to prevent chatter at the LOS output.

● No reference clock required

● Exceeds SONET/SDH requirements for jitter transfer/generation/tolerance

● Programmable jitter transfer bandwidth to support G.8251 OTN

● Programmable slice level

● Programmable LOS threshold via I²C

● I²C to access optional features

● Loss of lock (LOL) indicator

● PRBS Generator/detector