●Product Details
●The ADP1740/ADP1741 are CMOS, low dropout linear regulators that operate from 1.6 V to 3.6 V and provide up to 2 A of output current. These low VIN / VOUT LDOs are ideal for regulation of nanometer FPGA geometries operating from 2.5V down to 1.8V I/O rails, and powering core voltages down to 0.75V. Using an advanced, proprietary architecture, the ADP1740/ADP1741 provide high power supply rejection ratio (PSRR) and low noise, and achieve excellent line and load transient response with only a small 4.7 μF ceramic output capacitor.
●The ADP1740 is available in seven fixed output voltage options. The ADP1741 is an adjustable version that allows output voltages ranging from 0.75 V to 3.3 V via an external divider. The ADP1740/ADP1741 allow an external soft start capacitor to be connected to program the startup. A digital power-good output allows power system monitors to check the health of the output voltage.
●The ADP1740/ADP1741 are available in a 16-lead, 4 mm × 4 mm LFCSP, making them not only very compact solutions, but also providing excellent thermal performance for applications that require up to 2 A of output current in a small, low profile footprint..
●Applications
● Server computers
● Memory components
● Telecommunications equipment
● Network equipment
● DSP/FPGA/microprocessor supplies
● Instrumentation equipment/data acquisition systems
●### Features and Benefits
● Maximum output current: 2 A
● Input voltage range: 1.6 V to 3.6 V
● Low shutdown current: 2 μA
● Low dropout voltage: 160 mV @ 2 A load
● Initial accuracy: ±1%
● Accuracy over line, load, and temperature: ±2%
● 7 fixed output voltage options with soft start:
●0.75 V to 2.5 V (ADP1740)
● Adjustable output voltage options with soft start: 0.75 V to 3.3 V (ADP1741)
● High PSRR
●65 dB @ 1 kHz
●65 dB @ 10 kHz
●54 dB @ 100 kHz
● 23 μV rms at 0.75 V output
● Stable with small 4.7 μF ceramic output capacitor
● Please see data sheet for additional features
Part 3D Model
