ADSP-2185NKSTZ-320 Datasheet PDF - ADI

● 12.5 ns Instruction cycle time @1.8 V (internal), 80 MIPS sustained performance

● Single-cycle instruction execution

● Single-cycle context switch

● 3-bus architecture allows dual operand fetches in every instruction cycle

● Multifunction instructions

● Power-down mode featuring low CMOS standby power dissipation with 200 CLKIN cycle recovery from power-down condition

● Low power dissipation in idle mode

● ADSP-2100 family code compatible (easy to use algebraic syntax), with instruction set extensions

● Up to 256K byte of on-chip RAM, configured

● Up to 48K words program memory RAM

● Up to 56K words data memory RAM

● Dual-purpose program memory for both instruction and data storage

● Independent ALU, multiplier/accumulator, and barrel shifter computational units

● Two independent data address generators

● Powerful program sequencer provides zero overhead looping conditional instruction execution

● Programmable 16-bit interval timer with prescaler

● 100-lead LQFP and 144-ball BGA