Part 3D Model

$ 0.411

CD40107BPWR Datasheet PDF - TI

Manufacturer:

Category:

Logic Gates

Case Package:

TSSOP-8

Description:

NAND Gate 2Element 2IN CMOS 8Pin TSSOP T/R

Pictures:

3D Model

Symbol

Footprint

Pinout

Product Pictures

Documentation:

CD40107BPWR Datasheet (17 Pages)

Package Outline Dimension on4 Page 6 Page 7 Page 10 Page

Package Footprint Pad Layout on11 Page

CD40107BPWR Datasheet PDF (17 Pages)

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CD40107BPWR Specifications

TYPE

DESCRIPTION

Mounting Style

Surface Mount

Number of Pins

8 Pin

Supply Voltage (DC)

3.00V ~ 18.0V

Case/Package

TSSOP-8

Number of Outputs

1 Output

Output Current

136 mA

Number of Circuits

2 Circuit

Number of Bits

2 Bit

Propagation Delay Max (tpd)

200 ns

Voltage Nodes

5.00 V, 10.0 V, 15.0 V

Power Dissipation

500 mW

Number of Gates

2 Gate

Number of Inputs

2 Input

Operating Temperature (Max)

125 ℃

Operating Temperature (Min)

-55 ℃

Supply Voltage

3V ~ 18V

Supply Voltage (Max)

18 V

Supply Voltage (Min)

3 V

View Datasheet >

CD40107BPWR Size & Package

TYPE

DESCRIPTION

Product Lifecycle Status

Active

Packaging

Tape & Reel (TR)

Size-Length

3 mm

Size-Width

4.4 mm

Size-Height

1.05 mm

Operating Temperature

-55℃ ~ 125℃

View Datasheet >

CD40107BPWR Environmental

CD40107BPWR Export Classifications

CD40107BPWR Function Overview

CD40107BPWR Documents

CD40107BPWR Datasheet

17 Pages / 1.33 MByte

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CD40107BPWR Datasheet PDF

NAND Gate 2Element 2IN CMOS 8Pin TSSOP T/R

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