CD74HC137E Datasheet PDF - TI

●The CD74HC137E is a 3-to-8 line high speed CMOS Decoder/Demultiplexer with address latches. It is well suited to memory address decoding or data routing applications. It features low power consumption usually associated with CMOS circuitry, yet has speeds comparable to low power Schottky TTL logic. It has three binary select inputs (A0, A1 and A2) that can be latched by an active LE signal to isolate the outputs from select-input changes. A "low" LE makes the output transparent to the input and the circuit functions as one-of-eight decoder. Two output enable inputs (OE1\ and OE0) are provided to simplify cascading and to facilitate demultiplexing. The demultiplexing function is accomplished by using the A0, A1, A2 inputs to select the desired output and using one of the other Output Enable inputs as the data input while holding the other Output Enable input in its active state.

● I/O Port or memory selector

● Two enable inputs to simplify cascading

● Balanced propagation delay and transition times

● Significant power reduction compared to LSTTL logic ICs

● High noise immunity

● Direct LSTTL input logic compatibility

● CMOS Input compatibility

● 10 LSTTL Load standard outputs

● 15 LSTTL Load bus driver outputs