CD74HC138M Datasheet PDF - TI

●The CD74HC138M is a 3-to-8 line high speed CMOS Decoder/Demultiplexer well suited to memory address decoding or data routing applications. It features low power consumption usually associated with CMOS circuitry, yet has speeds comparable to low power Schottky TTL logic. It has three binary select inputs (A0, A1 and A2). If the device is enabled, these inputs determine which one of the eight normally high outputs of the HC/HCT138 series will go low. Two active low and one active high enables (E1\, E2\ and E3) are provided to ease the cascading of decoders. The decoder"s 8 outputs can drive 10 low power Schottky TTL equivalent loads.

● I/O Port or memory selector

● Three enable inputs to simplify cascading

● Balanced propagation delay and transition times

● Significant power reduction compared to LSTTL logic ICs

● High noise immunity

● Direct LSTTL input logic compatibility

● CMOS Input compatibility

● 10 LSTTL Load standard outputs

● 15 LSTTL Load bus driver outputs

● Green product and no Sb/Br