CD74HC237M Datasheet PDF - TI

●The CD74HC237M is a 3-to-8 high speed CMOS Decoder/Demutiplexer with address latches. It is well suited to memory address decoding or data routing applications. Both circuits feature low power consumption usually associated with CMOS circuitry, yet have speeds comparable to low power Schottky TTL logic. It three binary select inputs (A0, A1 and A2) that can be latched by an active high LE signal to isolate the outputs from select-input changes. A "Low" LE makes the output transparent to the input and the circuit functions as one-of-eight decoder. Two Output Enable inputs (OE\1 and OE0) are provided to simplify cascading and to facilitate demultiplexing. The demultiplexing function is accomplished by using the A0, A1, A2 inputs to select the desired output and using one of the other Output Enable inputs as the data input while holding the other output enable input in its active state.

● I/O Port or memory selector

● Two enable inputs to simplify cascading

● Balanced propagation delay and transition times

● Significant power reduction compared to LSTTL logic ICs

● High noise immunity

● Direct LSTTL input logic compatibility

● CMOS Input compatibility

● 10 LSTTL Load standard outputs

● 15 LSTTL Load bus driver outputs

● Green product and no Sb/Br