CD74HC40103E Datasheet PDF - TI

●The CD74HC40103E is an 8-stage CMOS Synchronous Down Counter manufactured with high speed silicon gate technology and consist of a single output which is active when the internal count is zero. The 40103 contains a single 8-bit binary counter. Each has control inputs for enabling or disabling the clock, for clearing the counter to its maximum count and for presetting the counter either synchronously or asynchronously. All control inputs and the TC\ output are active-low logic. In normal operation, the counter is decremented by one count on each positive transition of the clock. Counting is inhibited when the TE\ input is high. The TC\ output goes low when the count reaches zero if the TE\ input is low and remains low for one full clock period. When the PE\ input is low, data at the P0-P7 inputs are clocked into the counter on the next positive clock transition regardless of the state of the TE\ input.

● Cascadable in synchronous or ripple mode

● Balanced propagation delay and transition times

● Significant power reduction compared to LSTTL logic ICs

● High noise immunity

● Direct LSTTL input logic compatibility

● CMOS Input compatibility

● 10 LSTTL Load standard outputs

● 15 LSTTL Loads bus driver outputs