CD74HC73E Datasheet PDF - TI

●The CD74HC73E is a high speed CMOS logic dual Negative-Edge-Triggered Flip-flop with J-K reset, clock inputs and Q and Q\ outputs. The CD74HCT73 utilize silicon gate CMOS technology to achieve operating speeds equivalent to LSTTL parts. It exhibits the low power consumption of standard CMOS integrated circuits, together with the ability to drive 10 LSTTL loads. They change state on the negative-going transition of the clock pulse. Reset is accomplished asynchronously by a low level input. This device is functionally identical to the HC/HCT107 but differs in terminal assignment and in some parametric limits. The HCT logic family is functionally as well as pin compatible with the standard LS logic family.

● Hysteresis on clock inputs for improved noise immunity and increased input rise and fall times

● Asynchronous reset

● Complementary outputs

● Buffered inputs

● Balanced propagation delay and transition times

● Significant power reduction compared to LSTTL logic ICs

● ±20mA DC input/output diode current

● ±25mA DC drain current