●Cypress’s EZ-USB FX2 is the world’s first USB 2.0 integrated microcontroller. By integrating the USB 2.0 transceiver, SIE, enhanced 8051 microcontroller, and a programmable peripheral interface in a single chip, Cypress has created a very cost-effective solution that provides superior time-to-market advantages. The ingenious architecture of FX2 results in data transfer rates of 56 Mbytes per second, the maximum allowable USB 2.0 bandwidth, while still using a low cost 8051 microcontroller in a package as small as a 56 SSOP. Because it incorporates the USB 2.0 transceiver, the FX2 is more economical, providing a smaller footprint solution than USB 2.0 SIE or external transceiver implementations. With EZ-USB FX2, the Cypress Smart SIE handles most of the USB 1.1 and 2.0 protocol in hardware, freeing the embedded micro controller for application-specific functions and decreasing development time to ensure USB compatibility. The General Programmable Interface (GPIF) and Master/Slave Endpoint FIFO (8- or 16-bit data bus) provides an easy and glueless interface to popular interfaces such as ATA, UTOPIA, EPP, PCMCIA, and most DSP/processors.
●EZ-USB FX2™ Features
●• Single-chip integrated USB 2.0 Transceiver, SIE, and Enhanced 8051 Microprocessor
●• Software: 8051 code runs from:
● — Internal RAM, which is downloaded via USB
● — Internal RAM, which is loaded from EEPROM
● — External memory device (128 pin package
●• Four programmable BULK/INTERRUPT/ISOCHRONOUS endpoints
● — Buffering options: double, triple and quad
●• 8- or 16-bit external data interface
●• GPIF
● — Allows direct connection to most parallel interface
● — Programmable waveform descriptors and configuration registers to define waveforms
● — Supports multiple Ready (RDY) inputs and Control (CTL) outputs
●• Integrated, industry standard enhanced 8051:
● — Up to 48-MHz clock rate
● — Four clocks per instruction cycle
● — Two USARTS
● — Three counter/timers
● — Expanded interrupt system
● — Two data pointers
●• Supports bus-powered applications by using renumeration
●• 3.3V operation
●• Smart Serial Interface Engine
●• Vectored USB interrupts
●• Separate data buffers for the SETUP and DATA portions of a CONTROL transfer
●• Integrated I2C-compatible controller, runs at 100 or 400 kHz
●• 48-MHz, 24-MHz, or 12-MHz 8051 operation
●• Four integrated FIFOs
● — Brings glue and FIFOs inside for lower system cost
● — Automatic conversion to and from 16-bit buses
● — Master or slave operation
● — FIFOs can use externally supplied clock or asyn chronous strobes
● — Easy interface to ASIC and DSP ICs
●• Special autovectors for FIFO and GPIF interrupts
●• Up to 40 general-purpose I/Os
●• Four package options—128-pin TQFP, 100-pin TQFP, 56-pin QFN and 56-pin SSOP
●• Four packages are defined for the family: 56 SSOP, 56 QFN, 100 TQFP, and 128 TQFP
●Applications
●• DSL modems
●• ATA interface
●• Memory card readers
●• Legacy conversion devices
●• Cameras
●• Scanners
●• Home PNA
●• Wireless LAN
●• MP3 players
●• Networking.
Part 3D Model
