Mounting Style
Surface Mount
Supply Voltage (DC)
5.00 V
Altera
66 Pages / 0.56 MByte
Altera
Programmable logic , 64 macrocells, 4 logic array blocks, 36 I/O pins, 10ns
Altera
CPLD MAX 7000S Family 1.25K Gates 64 Macro Cells 100MHz CMOS Technology 5V 44Pin PLCC
Altera
CPLD MAX 7000S Family 1.25K Gates 64 Macro Cells 100MHz CMOS Technology 5V 100Pin TQFP
Altera
CPLD MAX 7000 Family 1.25K Gates 64 Macro Cells 100MHz CMOS Technology 5V 44Pin PLCC
Altera
CPLD MAX 7000S Family 1.25K Gates 64 Macro Cells 166.7MHz CMOS Technology 5V 44Pin PLCC
Altera
CPLD MAX 7000A Family 1.25K Gates 64 Macro Cells 100MHz CMOS Technology 3.3V 44Pin TQFP
Altera
CPLD MAX 7000A Family 1.25K Gates 64 Macro Cells 135.1MHz CMOS Technology 3.3V 44Pin TQFP
Altera
CPLD MAX 7000 Family 1.25K Gates 64 Macro Cells 76.9MHz CMOS Technology 5V 84Pin PLCC
Altera
CPLD MAX 7000A Family 1.25K Gates 64 Macro Cells 135.1MHz CMOS Technology 3.3V 44Pin TQFP
Altera
Ic Cpld 64mc 15ns 68plcc Ic Cpld 64mc 15ns 68plcc Ic Cpld 64mc 15ns 68plcc Ic Cpld 64mc 15ns 68plcc
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