FDG6320C Datasheet PDF - ON Semiconductor

●The FDG6320C is a dual N/P-channel logic level enhancement-mode MOSFET with high cell density and DMOS technology. This very high density process is especially tailored to minimize ON-state resistance. This device has been designed especially for low voltage applications as a replacement for bipolar digital transistors and small signal MOSFETs. Since bias resistors are not required, this dual digital FET can replace several different digital transistors, with different bias resistor values.

● Very small package outline

● Very low level gate drive requirements allowing direct operation in 3V circuits (VGS (th) <1.5V)

● Gate-source Zener for ESD ruggedness