GAL16V8D-25LP Datasheet PDF - Lattice Semiconductor

●Description

●The GAL16V8, at 3.5 ns maximum propagation delay time, combines a high performance CMOS process with Electrically Erasable (E2) floating gate technology to provide the highest speed performance available in the PLD market. High speed erase times (<100ms) allow the devices to be reprogrammed quickly and efficiently.

●Features

●•HIGH PERFORMANCE E2CMOS®TECHNOLOGY

●—3.5 ns Maximum Propagation Delay

●—Fmax = 250 MHz

●—3.0 ns Maximum from Clock Input to Data Output

●—UltraMOS® Advanced CMOS Technology

●•50% to 75% REDUCTION IN POWER FROM BIPOLAR

●—75mA Typ Icc on Low Power Device

●—45mA Typ Icc on Quarter Power Device

●•ACTIVE PULL-UPS ON ALL PINS

●•E2CELL TECHNOLOGY

●—Reconfigurable Logic

●—Reprogrammable Cells

●—100% Tested/100% Yields

●—High Speed Electrical Erasure (<100ms)

●—20 Year Data Retention

●•EIGHT OUTPUT LOGIC MACROCELLS

●—Maximum Flexibility for Complex Logic Designs

●—Programmable Output Polarity

●—Also Emulates 20-pin PAL® Devices with Full Function/Fuse Map/Parametric Compatibility

●•PRELOAD AND POWER-ON RESET OF ALL REGISTERS

●—100% Functional Testability

●•APPLICATIONS INCLUDE:

●—DMA Control

●—State Machine Control

●—High Speed Graphics Processing

●—Standard Logic Speed Upgrade

●•ELECTRONIC SIGNATURE FOR IDENTIFICATION