IS42S16400J-7TLI Datasheet PDF - Integrated Silicon Solution(ISSI)

●The IS42S16400J-7TLI is a 64MB Synchronous DRAM is organized as 1,048,576 bits x 16 bits x 4-bank for improved performance. The synchronous DRAMs achieve high-speed data transfer using pipeline architecture. All inputs and outputs signals refer to the rising edge of the clock input. The 64MB SDRAM is a high speed CMOS, dynamic random-access memory designed to operate in 3.3V memory systems containing 67,108,864 bits. Internally configured as a quad-bank DRAM with a synchronous interface. Each 16,777,216 bit bank is organized as 4,096 rows by 256 columns by 16 bits. The 64MB SDRAM includes an AUTO REFRESH MODE and a power-saving, power-down mode. All signals are registered on the positive edge of the clock signal, CLK. All inputs and outputs are LVTTL compatible.

● Synchronous with 3.3V Power Supply

● LVTTL Interface

● Programmable Burst Length (1, 2, 4, 8, Full Page)

● Sequential/Interleave Programmable Burst Sequence

● Self Refresh and Auto Refresh Modes

● Random Column Address Every Clock Cycle

● Programmable CAS Latency (2, 3 Clocks)

● Burst Read/Write and Burst Read/Single Write

● Long-term Support

● 200, 166, 143 and 133MHz Clock Frequency

● Fully Synchronous, All Signals Referenced to a Positive Clock Edge

● Internal Bank for Hiding Row Access/Pre-charge

● 4096 Refresh Cycles Every 64ms (Com, Ind, A1 Grade) or 16ms (A2 Grade)

●Stress greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device.