K4B4G0846B-MCH9 Datasheet PDF - Samsung

●The DDP 4Gb DDR3 SDRAM B-die is organized as a 128Mbit x 4 I/Os x 8banks, 64Mbit x 8 I/Os x 8banks. This synchronous device achieves high speed double-data-rate transfer rates of up to 1333Mb/sec/pin (DDR3-

●1333) for general applications.

●The chip is designed to comply with the following key DDR3 SDRAM features such as posted CAS, Programmable CWL, Internal (Self) Calibration, On Die Termination using ODT pin and Asynchronous Reset .

●• JEDEC standard 1.5V ± 0.075V Power Supply

●• VDDQ = 1.5V ± 0.075V

●• 400 MHz fCK for 800Mb/sec/pin, 533MHz fCK for 1066Mb/sec/pin,

●667MHz fCK for 1333Mb/sec/pin

●• 8 Banks

●• Posted CAS

●• Programmable CAS Latency(posted CAS): 6, 7, 8, 9, 10

●• Programmable Additive Latency: 0, CL-2 or CL-1 clock

●• Programmable CAS Write Latency (CWL) = 5 (DDR3-800), 6 (DDR3-1066) and 7 (DDR3-1333)

●• 8-bit pre-fetch

●• Burst Length: 8 (Interleave without any limit, sequential with starting address “000” only), 4 with tCCD = 4 which does not allow seamless read or write [either On the fly using A12 or MRS]

●• Bi-directional Differential Data-Strobe

●• Internal(self) calibration : Internal self calibration through ZQ pin (RZQ : 240 ohm ± 1%)

●• On Die Termination using ODT pin

●• Average Refresh Period 7.8us at lower than TCASE 85°C, 3.9us at 85°C < TCASE < 95 °C

●• Asynchronous Reset

●• Package : 78 balls FBGA - x4/x8

●• All of Lead-Free products are compliant for RoHS

●• All of products are Halogen-free