LAN7500-ABZJ Datasheet PDF - Microchip

●The LAN7500-ABZJ is a Hi-Speed USB 2.0 to 10/100/1000 Ethernet Controller contains an integrated 10/100/1000 Ethernet MAC and PHY, filtering engine, USB PHY, Hi-speed USB 2.0 device controller, TAP controller, EEPROM controller and a FIFO controller with a total of 32kB of internal packet buffering. The internal USB 2.0 device controller and USB PHY are compliant with the USB 2.0 Hi-Speed standard. The device implements control, interrupt, bulk-in and bulk-out USB endpoints. The Ethernet controller supports auto-negotiation, auto-polarity correction, HP Auto-MDIX and is compliant with the IEEE 802.3, IEEE 802.3u, IEEE 802.3ab standards. ARP and NS offload is also supported. Multiple power management features are provided, including various low power modes and "Magic Packet", "Wake On LAN" and "Link Status Change" wake events. These wake events can be programmed to initiate an USB remote wakeup.

● Single chip Hi-speed USB 2.0 to 10/100/1000 Ethernet controller

● 10/100/1000 Ethernet MAC with full-duplex support

● 10/100/1000 Ethernet PHY with HP Auto-MDIX

● Implements reduced power operating modes

● Supports EEPROM-less

● Operation for reduced BOM

● NetDetach provides automatic USB attach/detach when Ethernet cable is connected/removed

● Four endpoints supported

● Supports vendor specific commands

● Remote wakeup supported

● Full-duplex flow control

● Preamble generation and removal

● Automatic 32-bit CRC generation and checking

● 9kB Jumbo frame support

● Automatic payload padding and pad removal

● Loop-back modes