LP2996MR/NOPB Datasheet PDF - TI

●The LP2996MR/NOPB is a Linear Regulator designed to meet the JEDEC SSTL-2 specifications for termination of DDR-SDRAM. The device contains a high-speed operational amplifier to provide excellent response to load transients. The output stage prevents shoot through while delivering 1.5A continuous current and transient peaks up to 3A in the application as required for DDR-SDRAM termination. The device also incorporates a VSENSE pin to provide superior load regulation and a VREF output as a reference for the chipset and DIMMs. An additional feature found on the device is an active low shutdown (SD) pin that provides suspend to RAM (STR) functionality. When SD is pulled low the VTT output will tri-state providing a high impedance output, but, VREF will remain active. A power savings advantage can be obtained in this mode through lower quiescent current.

● Source and sink current

● Low output voltage offset

● No external resistors required

● Linear topology

● Low external component count

● Thermal shutdown

● Green product and no Sb/Br