LPC2129FBD64 Datasheet PDF - NXP

●General description

●The LPC2109/2119/2129 are based on a 16/32-bit ARM7TDMI-S CPU with real-time emulation and embedded trace support, together with 64/128/256 kB of embedded high-speed flash memory. A 128-bit wide memory interface and a unique accelerator architecture enable 32-bit code execution at maximum clock rate. For critical code size applications, the alternative 16-bit Thumb mode reduces code by more than 30 % with minimal performance penalty.

●Key features brought by LPC2109/2119/2129/01 devices

●■ Fast GPIO ports enable port pin toggling up to 3.5 times faster than the original device. They also allow for a port pin to be read at any time regardless of its function.

●■ Dedicated result registers for ADC(s) reduce interrupt overhead. The ADC pads are 5 V tolerant when configured for digital I/O function(s).

●■ UART0/1 include fractional baud rate generator, auto-bauding capabilities and handshake flow-control fully implemented in hardware.

●■ Buffered SSP serial controller supporting SPI, 4-wire SSI, and Microwire formats.

●■ SPI programmable data length and master mode enhancement.

●■ Diversified Code Read Protection (CRP) enables different security levels to be implemented. This feature is available in LPC2109/2119/2129/00 devices as well.

●■ General purpose timers can operate as external event counters.