●56F8013/56F8011 Description
●The 56F8013/56F8011 is a member of the 56800E core-based family of Digital Signal Controllers (DSCs). It combines, on a single chip, the processing power ofa DSP and the functionality of a microcontroller with a flexible set of peripherals to create an extremely cost-effective solution. Because of its low cost, configuration flexibility, and compact program code, the 56F8013/56F8011 is well-suited for many applications.
●56F8013/56F8011 Features
●Digital Signal Controller Core
●• Efficient 16-bit 56800E family Digital Signal Controller (DSC) engine with dual Harvard architecture
●• As many as 32 Million Instructions Per Second (MIPS) at 32MHz core frequency
●• Single-cycle 16 ×16-bit parallel Multiplier-Accumulator (MAC)
●• Four 36-bit accumulators, including extension bits
●• 32-bit arithmetic and logic multi-bit shifter
●• Parallel instruction set withunique DSP addressing modes
●• Hardware DO and REP loops
●• Three internal address buses
●• Four internal data buses
●• Instruction set supports both DSP and controller functions
●• Controller-style addressing modes and instructions for compact code
●• Efficient C compiler and local variable support
●• Software subroutine and interrupt stack with depth limited only by memory
●• JTAG/Enhanced On-Chip Emulation (OnCE) for unobtrusive, processor speed-independent, real-time debugging
●Memory
●• Dual Harvard architecture permits as many as three simultaneous accesses to program and data memory
●• Flash security and protection that prevent unauthorized users from gaining access to the internal Flash
●• On-chip memory:
●— 16KB of Program Flash (56F8013 device)
●12KB of Program Flash (56F8011 device)
●— 4KB of Unified Data/Program RAM (56F8013 device)
●2KB of Unified Data/ProgramRAM (56F8011 device)
●• EEPROM emulation capability using Flash
●Peripheral Circuits for 56F8013/56F8011
●• One multi-function six-output Pulse Width Modulator (PWM) module
●— Up to 96MHz PWM operating clock
●— 15 bits of resolution
●— Center-aligned and Edge-aligned PWM signal mode
●— Four programmable fault inputs with programmable digital filter
●— Double-buffered PWM registers
●— Each complementary PWM signal pair can outputdifferent switching frequency by selecting PWM generation sources from:
●– PWM generator
●– External GPIO
●– Internal timers
●– ADC conversion resultof over/under limits:
●– When the conversion result is greater than high limit, deactivate PWM signal
●– When the conversion result is less than low limit, activate the PWM signal
●• Two independent 12-bit Analog-to-Digital Converters (ADCs)
●— 2 x 3 channel inputs
●— Supports both simultaneous and sequential conversions
●— ADC conversions can be synchronized by both PWM and timer modules
●— Sampling rate up to 2.67MSPS
●— 8-word result buffer registers
●— ADC Smart Power Management (Auto-standby, auto-powerdown)
●• One 16-bit multi-purpose Quad Timer module (TMR)
●— Up to 96MHz operating clock
●— Four independent 16-bit counter/timers with cascading capability
●— Each timer has capture and compare capability
●— Up to 12 operating modes
●• One Serial Communication Interface (SCI) with LIN Slave functionality
●— Full-duplex or single-wire operation
●— Two receiver wake-up methods:
●– Idle line
●– Address mark
●• One Serial Peripheral Interface (SPI)
●— Full-duplex operation
●— Master and slave modes
●— Programmable Length Transactions (2 to 16 bits)
●• One Inter-Integrated Circuit (I2C) port
●— Operates up to 400kbps
●— Supports both master and slave operation
●• Computer Operating Properly (COP)/Watchdog timer capable of selecting different clock sources
Part 3D Model
