●INTRODUCTION
●The MC68030 is a second-generation full 32-bit enhanced microprocessor from Motorola.
●The MC68030 is a member of the M68000 Family of devices that combines a central processing unit (CPU) core, a data cache, an instruction cache, an enhanced bus controller, and a memory management unit (MMU) in a single VLSI device. The processor is designed to operate at clock speeds beyond 20 MHz. The MC68030 is implemented with 32-bit registers and data paths, 32-bit addresses, a rich instruction set, and versatile addressing modes.
●The MC68030 is upward object code compatible with the earlier members of the M68000 Family and has the added features of an on-chip MMU, a data cache, and an improved bus interface. It retains the flexible coprocessor interface pioneered in the MC68020 and provides full IEEE floating-point support through this interface with the MC68881 or MC68882 floating-point coprocessor. Also, the internal functional blocks of this microprocessor are designed to operate in parallel, allowing instruction execution to be overlapped. In addition to instruction execution, the internal caches, the on-chip MMU, and the external bus controller all operate in parallel.
●FEATURES
●The features of the MC68030 microprocessor are:
●• Object Code Compatible with the MC68020 and Earlier M68000 Microprocessors
●• Complete 32-Bit Nonmultiplexed Address and Data Buses
●• 16 32-Bit General-Purpose Data and Address Registers
●• Two 32-Bit Supervisor Stack Pointers and 10 Special-Purpose Control Registers
●• 256-Byte Instruction Cache and 256-Byte Data Cache Can Be Accessed Simultaneously
●• Paged MMU that Translates Addresses in Parallel with Instruction Execution and Internal Cache Accesses
●• Two Transparent Segments Allow Untranslated Access to Physical Memory To Be Dfined for Systems That Transfer Large Blocks of Data between Predefined Physical Addresses — e.g., Graphics Applications
●• Pipelined Architecture with Increased Parallelism Allows Accesses to Internal Caches To Occur in Parallel with Bus Transfers and Instruction Execution To Be Overlapped
●• Enhanced Bus Controller Supports Asynchronous Bus Cycles (three clocks minimum), Synchronous Bus Cycles (two clocks minimum), and Burst Data Transfers (one clock minimum) all to the Physical Address Space
●• Dynamic Bus Sizing Supports 8-, 16-, 32-Bit Memories and Peripherals
●• Support for Coprocessors with the M68000 Coprocessor Interface — e.g., Full IEEE Floating-Point Support Provided by the MC68881/MC68882 Floating-Point Coprocessors
●• 4-Gbyte Logical and Physical Addressing Range
●• Implemented in Motorola"s HCMOS Technology That Allows CMOS and HMOS (High Density NMOS) Gates to be Combined for Maximum Speed, Low Power, and Optimum Die Size
●• Processor Speeds Beyond 20 MHz
