MT41K128M16JT-125 XIT Datasheet PDF - Micron

●The MT41K128M16JT-125 XIT is a 1.35V DDR3L SDRAM is in low-voltage version of the 1.5V DDR3 SDRAM. Unless stated otherwise, the DDR3L SDRAM device meets the functional and timing specifications listed in the equivalent density standard or automotive DDR3 SDRAM.

● VDD = VDDQ = 1.35V (1.283 to 1.45V)

● Backward-compatible to VDD = VDDQ = 1.5V ±0.075V

● Differential Bidirectional Data Strobe

● 8n-bit Pre-fetch Architecture

● Differential Clock Inputs (CK, CK#)

● 8 Internal Banks

● Nominal and Dynamic On-die Termination (ODT) for Data, Strobe and Mask Signals

● Programmable CAS (READ) Latency (CL)

● Programmable Posted CAS Additive Latency (AL)

● Programmable CAS (WRITE) Latency (CWL)

● Fixed Burst Length (BL) of 8 and Burst Chop (BC) of 4 (Via Mode Register Set [MRS])

● Selectable BC4 or BL8 on-the-fly (OTF)

● Self Refresh Mode

● TC of 0 to +95°C, 64ms, 8192-cycle Refresh at 0 to +85°C, 32ms at +85 to +95°C

● Self Refresh Temperature (SRT)

● Automatic Self Refresh (ASR)

● Write Levelling

● Multipurpose Register

● Output Driver Calibration

● AEC-Q100 Qualified