MT46V32M16P-5B:J Datasheet PDF - Micron

●The MT46V32M16P-5B:J is a Double Data Rate (DDR) SDRAM uses double data rate architecture to achieve high-speed operation. The double data rate architecture is essentially 2n-prefetch architecture with an interface designed to transfer two data words per clock cycle at the I/O pins. A single read or write access for the DDR SDRAM effectively consists of a single 2n-bit-wide, one-clock-cycle data transfer at the internal DRAM core and two corresponding n-bit-wide, one-half-clock-cycle data transfers at the I/O pins. A bidirectional data strobe (DQS) is transmitted externally, along with data, for use in data capture at the receiver. DQS is a strobe transmitted by the DDR SDRAM during reads and by the memory controller during writes. DQS is edge-aligned with data for reads and centre-aligned with data for writes. The x16 offering has two data strobes, one for the lower -byte and one for the upper -byte.

● Differential clock inputs

● Commands entered on each positive CK edge

● DLL to align DQ and DQS transitions with CK

● Four internal banks for concurrent operation

● Auto refresh - 64ms, 8192-cycle

● Longer-lead TSOP for improved reliability (OCPL)

● Concurrent auto precharge option supported