NA555DR Datasheet PDF - TI

●The NA555DR is a Precision Timing Circuit, capable of producing accurate time delays or oscillation. In the time-delay or mono-stable mode of operation, the timed interval is controlled by a single external resistor and capacitor network. In the a-stable mode of operation, the frequency and duty cycle can be controlled independently with two external resistors and a single external capacitor. The threshold and trigger levels normally are two-thirds and one-third, respectively, of VCC. These levels can be altered by use of the control-voltage terminal. When the trigger input falls below the trigger level, the flip-flop is set and the output goes high. If the trigger input is above the trigger level and the threshold input is above the threshold level, the flip-flop is reset and the output is low. The reset (RESET) input can override all other inputs and can be used to initiate a new timing cycle. When RESET goes low, the flip-flop is reset and the output goes low.

● Timing from microseconds to hours

● Astable or monostable operation

● Adjustable duty cycle

● TTL-compatible output can sink or source up to 200mA

● Green product and no Sb/Br

●IC can be damaged by ESD. We recommend that all ICs be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.