●SUMMARY DESCRIPTION
●The NAND Flash 528 Byte/ 264 Word Page is a family of non-volatile Flash memories that uses
●the Single Level Cell (SLC) NAND cell technology. It is referred to as the Small Page family. The de
●vices range from 128Mbits to 1Gbit and operate with either a 1.8V or 3V voltage supply. The size of a Page is either 528 Bytes (512 + 16 spare) or 264 Words (256 + 8 spare) depending on whether the
●device has a x8 or x16 bus width.
●FEATURES SUMMARY
●■ HIGH DENSITY NAND FLASH MEMORIES
●– Up to 1 Gbit memory array
●– Up to 32 Mbit spare area
●– Cost effective solutions for mass storage applications
●■ NAND INTERFACE
●– x8 or x16 bus width
●– Multiplexed Address/ Data
●– Pinout compatibility for all densities
●■ SUPPLY VOLTAGE
●– 1.8V device: VDD = 1.7 to 1.95V
●– 3.0V device: VDD = 2.7 to 3.6V
●■ PAGE SIZE
●– x8 device: (512 + 16 spare) Bytes
●– x16 device: (256 + 8 spare) Words
●■ BLOCK SIZE
●– x8 device: (16K + 512 spare) Bytes
●– x16 device: (8K + 256 spare) Words
●■ PAGE READ / PROGRAM
●– Random access: 12µs (max)
●– Sequential access: 50ns (min)
●– Page program time: 200µs (typ)
●■ COPY BACK PROGRAM MODE
●– Fast page copy without external buffering
●■ FAST BLOCK ERASE
●– Block erase time: 2ms (Typ)
●■ STATUS REGISTER
●■ ELECTRONIC SIGNATURE
●■ CHIP ENABLE ‘DON’T CARE’ OPTION
●– Simple interface with microcontroller
●■ SERIAL NUMBER OPTION
●■ HARDWARE DATA PROTECTION
●– Program/Erase locked during Power transitions
●■ DATA INTEGRITY
●– 100,000 Program/Erase cycles
●– 10 years Data Retention
●■ RoHS COMPLIANCE
●– Lead-Free Components are Compliant with the RoHS Directive
●■ DEVELOPMENT TOOLS
●– Error Correction Code software and hardware models
●– Bad Blocks Management and Wear Leveling algorithms
●– File System OS Native reference software
●– Hardware simulation models
Part 3D Model
