NB100LVEP91DWR2G Datasheet PDF - ON Semiconductor

●The NB100LVEP91 is a triple input to NECL output translator. The device accepts LVPECL, LVTTL, HSTL, CML or LVDS signals, and translates them to differential -2.5 V / -3.3 V NECL output signals.To accomplish the level translation, the LVEP91 requires three power rails. The V supply should be connected to the positive supply, and the VEE pin should be connected to the negative power supply. The GNDI pins are connected to the system ground plane. Both V should be bypassed to ground via 0.01 uF capacitors.Under open input conditions, the Dbar input will be biased at V/2 and the D input will be pulled to GND. This condition will force the Q output to a low, ensuring stability. pin, an internally generated voltage supply, is available to this device only. For single-ended input conditions, the unused differential input is connected to V as a switching reference voltage. V may also rebias AC coupled inputs. When used, decouple V via a 0.01 uF capacitor and limit current sourcing or sinking to 0.5 mA. When not used, V

●Features |   | Benefits

●---|---|---

● | |  | |  |

● Typical Maximum Frequency >2 GHz

●|   |

● Design Flexibility

● 430 ps Typical Propagation Delay

●|   |  

● Operating Range: VCC = 2.375 V to 3.8 V; VEE = -2.375 V to -3.8 V; GNDI = 0 V

●|   |  

● Q Output will default LOW with Inputs Open or at GND

●|   |  

● Pb-Free Packages are Available

●|   |