NB3N3020DTG Datasheet PDF - ON Semiconductor

●The NB3N3020DTG is a low-phase noise selectable Clock Multiplier takes a 5 to 27MHz fundamental mode parallel resonant crystal or a 2 to 210MHz LVCMOS single ended clock source and generates a differential LVPECL output and a single ended LVCMOS/LVTTL output at a selectable clock output frequency which is a multiple of the input clock frequency. Three tri-level (low, mid, high) LVCMOS/LVTTL single ended select pins set one of 26 possible clock multipliers. The LVCMOS/LVTTL output enable (OE1) tri-states the LVCMOS/LVTTL clock output (CLK1) when low. When the LVTTL/LVCMOS output enable (OE2) is LOW, LVPECL CLK2 is forced LOW and LVPECL CLK2 is forced HIGH.

● External loop filter is not required

● LVPECL Differential output

● LVCMOS/LVTTL outputs

● RMS period jitter of 5ps