●The Texas Instruments PCI1520, a 208-terminal dual-slot CardBus controller designed to meet the _PCI Bus Power Management Interface Specification for PCI to CardBus Bridges_, is an ultralow-power high-performance PCI-to-CardBus controller that supports two independent card sockets compliant with the _PC Card Standard_ (rev. 7.1). The PCI1520 provides features that make it the best choice for bridging between PCI and PC Cards in both notebook and desktop computers. The _1997 PC Card Standard_ retains the 16-bit PC Card specification defined in _PCI Local Bus Specification_ and defines the new 32-bit PC Card, CardBus, capable of full 32-bit data transfers at 33 MHz. The PCI1520 supports any combination of 16-bit and CardBus PC Cards in the two sockets, powered at 5 V or 3.3 V, as required.
●The PCI1520 is compliant with the _PCI Local Bus Specification_, and its PCI interface can act as either a PCI master device or a PCI slave device. The PCI bus mastering is initiated during CardBus PC Card bridging transactions. The PCI1520 is also compliant with _PCI Bus Power Management Interface Specification_ (rev. 1.1).
●All card signals are internally buffered to allow hot insertion and removal without external buffering. The PCI1520 is register-compatible with the Intel 82365SL-DF and 82365SL ExCA controllers. The PCI1520 internal data path logic allows the host to access 8-, 16-, and 32-bit cards using full 32-bit PCI cycles for maximum performance. Independent buffering and a pipeline architecture provide an unsurpassed performance level with sustained bursting. The PCI1520 can also be programmed to accept fast posted writes to improve system-bus utilization.
●Multiple system-interrupt signaling options are provided, including parallel PCI, parallel ISA, serialized ISA, and serialized PCI. Furthermore, general-purpose inputs and outputs are provided for the board designer to implement sideband functions. Many other features designed into the PCI1520, such as socket activity light-emitting diode (LED) outputs, are discussed in detail throughout the design specification.
●An advanced complementary metal-oxide semiconductor (CMOS) process achieves low system power consumption while operating at PCI clock rates up to 33 MHz. Several low-power modes enable the host power management system to further reduce power consumption.
Part 3D Model
