●The SMJ320C50KGD digital signal processor (DSP) is a high-performance, 16-bit, fixed-point processor manufactured in 0.64-um double-level metal CMOS technology.
●The SMJ320C50 KGD employs the hot-chuck-probe process. This process uses standard probed product that is tested again, this time at full data sheet specifications, in wafer form at speed and elevated temperature (125°C). Each individual die is then sawed, inspected, and packaged for shipment.
●A number of enhancements to the basic "C2x architecture give the "C50 a minimum 2x performance over the previous generation. A four-deep instruction pipeline, which incorporates delayed branching, delayed call to a subroutine, and delayed return from a subroutine, allows the "C50 to perform instructions in fewer cycles. The addition of a PLU gives the "C50 a method of manipulating bits in data memory without using the ACC and the ALU. The "C50 has additional shifting and scaling capabilities for proper alignment of multiplicands or for storage of values to data memory.
●With the addition of the IDLE2 instruction, the "C50 achieves low-power consumption. IDLE2 removes the functional clock from the internal hardware of the "C50 that puts it into a total-sleep mode using only 5 uA. A low-logic level on an external interrupt with a chip duration of at least five clock cycles ends the IDLE2 mode.
●For electrical and timing specifications, see the _SMJ320C50/SMQ320C50 Digital Signal Processors _data sheet (literature number SGUS020).
● Processed to MIL-PRF-38535
● Fast Instruction Cycle Time of 30 ns and
●40 ns
● Source-Code Compatible With all "C1x and "C2x Devices
● RAM-Based Operation
● 9K-Word × 16-Bit Dual-Access On-Chip Program/Data RAM
● 1056-Word × 16-Bit Dual-Access On-Chip Data RAM
● 2K-Word × 16-Bit On-Chip Boot ROM
● 224K-Word × 16-Bit Maximum Addressable External Memory Space (64K-Word Program, 64K-Word Data, 64K-Word I/O, and 32K-Word Global)
● 32-Bit Arithmetic Logic Unit (ALU)
● 32-Bit Accumulator (ACC)
● 32-Bit Accumulator Buffer (ACCB)
● 16-Bit Parallel Logic Unit (PLU)
● 16 × 16-Bit Multiplier, 32-Bit Product
● Eleven Context Switch Registers
● Two Buffers for Circular Addressing
● Full-Duplex Synchronous Serial Port
● Time-Division Multiplexed (TDM) Serial Port
● Timer With Control and Counter Registers
● Sixteen Software-Programmable Wait-State Generators
● Divide-By-1 Clock Option
● IEEE Standard 1149.1 (JTAG) Test-Access Port
● Operations are Fully Static
● Fabricated Using the Texas Instruments (TI) Enhanced Performance Implanted CMOS (EPICTM) 0.64-um Technology
● Military Operating Temperature Range
●-55°C to 125°C
●IEEE Standard 1149.1-1990, IEEE Standard Test-Access Port and Boundary-Scan Architecture
●EPIC is a trademark of Texas Instruments.
