●Introduction
●This section provides a summary of each device’s features, lists the pin assignments, and describes the function of each pin. This document also provides detailed descriptions of peripherals, electrical specifications, parameter measurement information, and mechanical data about the available packaging.
●Features
●• High-Performance Static CMOS Technology
●– 150 MHz (6.67-ns Cycle Time)
●– Low-Power (1.8-V Core at 135 MHz, 1.9-V Core at 150 MHz, 3.3-V I/O) Design
●• JTAG Boundary Scan Support(1)
●• High-Performance 32-Bit CPU ( TMS320C28x™)
●– 16 x 16 and 32 x 32 MAC Operations
●– 16 x 16 Dual MAC
●– Harvard Bus Architecture
●– Atomic Operations
●– Fast Interrupt Response and Processing
●– Unified Memory Programming Model
●– 4M Linear Program/Data Address Reach
●– Code-Efficient (in C/C++ and Assembly)
●– TMS320F24x/LF240x Processor Source Code Compatible
●• On-Chip Memory
●– Flash Devices: Up to 128K x 16 Flash (Four 8K x 16 and Six 16K x 16 Sectors)
●– ROM Devices: Up to 128K x 16 ROM
●– 1K x 16 OTP ROM
●– L0 and L1: 2 Blocks of 4K x 16 Each Single-Access RAM (SARAM)
●– H0: 1 Block of 8K x 16 SARAM
●– M0 and M1: 2 Blocks of 1K x 16 Each SARAM
●• Boot ROM (4K x 16)
●– With Software Boot Modes
●– Standard Math Tables
●• External Interface (2812)
●– Over 1M x 16 Total Memory
●– Programmable Wait States
●– Programmable Read/Write Strobe Timing
●– Three Individual Chip Selects
●• Endianness: Little Endian
●• Clock and System Control
●– Dynamic PLL Ratio Changes Supported
●– On-Chip Oscillator
●– Watchdog Timer Module
●• Three External Interrupts
●• Peripheral Interrupt Expansion (PIE) Block That Supports 45 Peripheral Interrupts
●• Three 32-Bit CPU-Timers
●• 128-Bit Security Key/Lock
●– Protects Flash/ROM/OTP and L0/L1 SARAM
●– Prevents Firmware Reverse-Engineering
●• Motor Control Peripherals
●– Two Event Managers (EVA, EVB)
●– Compatible to 240xA Devices
●• Serial Port Peripherals
●– Serial Peripheral Interface (SPI)
●– Two Serial Communications Interfaces (SCIs), Standard UART
●– Enhanced Controller Area Network (eCAN)
●– Multichannel Buffered Serial Port (McBSP)
●• 12-Bit ADC, 16 Channels
●– 2 x 8 Channel Input Multiplexer
●– Two Sample-and-Hold
●– Single/Simultaneous Conversions
●– Fast Conversion Rate: 80 ns/12.5 MSPS
●• Up to 56 General-Purpose I/O (GPIO) Pins
●• Advanced Emulation Features
●– Analysis and Breakpoint Functions
●– Real-Time Debug via Hardware
●• Development Tools Include
●– ANSI C/C++ Compiler/Assembler/Linker
●– Code Composer Studio™ IDE
●– DSP/BIOS™
●– JTAG Scan Controllers(1)
●• Low-Power Modes and Power Savings
●– IDLE, STANDBY, HALT Modes Supported
●– Disable Individual Peripheral Clocks
Part 3D Model
