SN65LVDS388ADBT Datasheet PDF - TI

●The SN65LVDS388ADBT is a differential Line Receiver implements the electrical characteristics of low-voltage differential signalling (LVDS). This signalling technique lowers the output voltage levels of 5V differential standard levels (such as EIA/TIA-422B) to reduce the power, increase the switching speeds and allow operation with a 3V supply rail. Any of the differential receivers provides a valid logical output state with a ±100mV differential input voltage within the input common-mode voltage range. The input common-mode voltage range allows 1V of ground potential difference between two LVDS nodes. Additionally, the high-speed switching of LVDS signals almost always requires the use of a line impedance matching resistor at the receiving end of the cable or transmission media. The LVDT products eliminate this external resistor by integrating it with the receiver.

● Open-circuit failsafe

● Flow-through pin-out

● Integrated 110R line termination resistors on LVDT products

● Bus-terminal ESD exceeds 15kV

● LVTTL levels are 5V tolerant

● 2.6ns Typical propagation delay time

● 100ps Typical output skew

● <1ns Typical part-to-part skew

● Green product and no Sb/Br