SN74AUP1T97DSFR Datasheet PDF - TI

●DESCRIPTION/ORDERING INFORMATION

●AUP technology is the industry"s lowest-power logic technology designed for use in battery-operated or battery backed-up equipment. The SN74AUP1T97 is designed for logic-level translation applications with input switching levels that accept 1.8-V LVCMOS signals, while operating from either a single 3.3-V or 2.5-V VCC supply.

●FEATURES

●• Available in the Texas Instruments NanoStar™ Packages

●• Single-Supply Voltage Translator

●• 1.8 V to 3.3 V (at VCC= 3.3 V)

●• 2.5 V to 3.3 V (at VCC= 3.3 V)

●• 1.8 V to 2.5 V (at VCC= 2.5 V)

●• 3.3 V to 2.5 V (at VCC= 2.5 V)

●• Nine Configurable Gate Logic Functions

●• Schmitt-Trigger Inputs Reject Input Noise and Provide Better Output Signal Integrity

●• Ioff Supports Partial-Power-Down Mode With Low Leakage Current (0.5 µA)

●• Very Low Static and Dynamic Power Consumption

●• Pb-Free Packages Available: SON (DRY or DSF), SOT-23 (DBV), SC-70 (DCK), and NanoStar WCSP

●• Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II

●• ESD Performance Tested Per JESD 22

●– 2000-V Human-Body Model(A114-B, Class II)

●– 1000-V Charged-Device Model (C101)

●• Related Devices: SN74AUP1T98, SN74AUP1T57, and SN74AUP1T58