SN74HC165D Datasheet PDF - TI

●The SN74HC165D is a 8-bit Parallel-load Shift Register features a clock-inhibit (CLK INH) function and a complementary serial (QH) output. The 8-bit parallel-load shift register that, when clocked, shift the data toward a serial (QH) output. Parallel-in access to each stage is provided by eight individual direct data (A-H) inputs that are enabled by a low level at the shift/load (SH/LD) input. Clocking is accomplished by a low-to-high transition of the clock (CLK) input while SH/LD is held high and CLK INH is held low. The functions of CLK and CLK INH are interchangeable. Since a low CLK and a low-to-high transition of CLK INH also accomplish clocking, CLK INH should be changed to the high level only while CLK is high. Parallel loading is inhibited when SH/LD is held high. While SH/LD is low, the parallel inputs to the register are enabled independently of the levels of the CLK, CLK INH or serial (SER) inputs.

● Outputs can drive up to 10 LSTTL loads

● Low power consumption, 80µA maximum ICC

● 13ns Typical TPD

● ±4mA Output drive at 5V

● Low input current of 1µA (maximum)

● Complementary outputs

● Direct overriding load (data) inputs

● Gated clock inputs

● Parallel-to-serial data conversion

● Green product and no Sb/Br