SN74HC373PWR Datasheet PDF - TI

●The SN74HC373PWR is an octal transparent D Latch with 3-state outputs. It is designed specifically for driving highly capacitive or relatively low-impedance loads. It is particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers and working registers. While the LE input is high, the Q outputs follow the data (D) inputs. When LE is taken low, the Q outputs are latched at the levels that were set up at the D inputs. An OE\ input places the eight outputs in either a normal logic state (high or low logic levels) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines without interface or pull-up components. OE\ does not affect the internal operations of the latches. Old data can be retained or new data can be entered while the outputs are off.

● High-current 3-state true outputs can drive up to 15 LSTTL loads

● Full parallel access for loading

● Eight high-current latches

● 80µA Maximum low power consumption

● Typical tpd = 13ns

● ±6mA Output drive at 5V

● 1µA Maximum low input current

● Green product and no Sb/Br