SN74LVC126ADR Datasheet PDF - TI

●The SN74LVC126ADR is a quadruple Bus Buffer Gate with 3-state outputs and is designed for 1.65V to 3.6V VCC operation. The SN74LVC126A features independent line drivers with 3-state outputs. Each output is disabled when the associated output-enable (OE) input is low. To ensure the high-impedance state during power up or power down, OE should be tied to GND through a pull-down resistor and the minimum value of the resistor is determined by the current-sourcing capability of the driver. Inputs can be driven from either 3.3/5V devices. This feature allows the use of this device as a translator in a mixed 3.3/5V system environment.

● Latch-up performance exceeds 250mA per JESD 17

● Inputs accept voltages to 5.5V

● 4.7ns at 3.3V Propagation delay (tpd)

● <0.8V at VCC = 3.3V, TA = 25°C VOLP (output ground bounce)

● >2V at VCC = 3.3V, TA = 25°C VOHV (output VOH undershoot)

● Green product and no Sb/Br